1. Field of the Invention
This invention relates generally to computer systems and more specifically to a technique for ensuring circuit devices are not overstressed by operating voltages above their rated tolerance.
2. Description of the Related Art
In a typical processor device, such as a central processor unit (CPU) or graphics processing unit (GPU), different logic portions may be powered from different supply voltages. For example, in a GPU, core processing logic that processes data and generates command signals to external devices (e.g., memory devices) may be powered from a first supply voltage (e.g., VDD), while input output (I/O) logic that drives those command signals onto I/O pads may be powered from a second supply voltage (e.g., VDDP). In an effort to conserve power and increase operating frequency, the supply voltage used to power the core logic may be lower than the supply voltage used to power the I/O logic.
In some cases, I/O pad logic may include a programmable voltage regulator allowing operating voltages of I/O pad drivers to be adjusted, for example, to ensure optimal I/O performance. The regulator generates regulated voltages to the I/O drivers so that the allowable I/O power supply level can be extended. Signals from the core logic control may be used to program and configure the regulator so that regulated outputs are optimal levels.
Unfortunately, during power up or power down of the device, the I/O supply voltage may reach its final value while the core supply voltage is still ramping up or is completely off. Under such conditions, control signals supplied by the core logic to configure the programmable voltage controller may be at undefined logic levels. As a result, the regulator may be inadvertently configured in an unknown and, possibly, less than optimal manner. This situation may cause the regulated voltages output by the regulator and internal bias levels (inside of regulator) to be much higher than the maximum tolerance levels of these devices. This type of overstressing may lead to immediate or premature device failure.
In some conventional systems, this situation has been addressed by utilizing external components to ensure a proper power sequence is achieved. For example, circuit components may be arranged to ensure the core logic supply voltage supplied to the device has reached a final level before the I/O logic supply voltage is supplied to the device. However, this approach is also suboptimal as it adds components to the system bill of materials (BOMs) and increases overall cost and complexity.
Accordingly, what is needed is an improved technique to avoid the problems encountered when core logic and I/O logic supply voltages reach final voltage levels at different times.